1. Field of the Invention
This invention is related to the field of processors and, more particularly, to multithreaded processors and maintaining program counters (PCs) for instructions in processor such as multithreaded processors.
2. Description of the Related Art
In a typical processor, the PC of each instruction in the pipeline is tracked in some fashion. The PC may be used by some instructions during execution, such as relative control transfer instructions which calculate a target address using the PC of the relative control transfer instruction and one or more operands of the relative control transfer instruction. Additionally, the PC is needed to provide for precise interrupts/exceptions in a processor. That is, if an instruction experiences an interrupt/exception during execution, the PC of the instruction is used to identify the instruction for the interrupt/exception handler. As address spaces increase in size (e.g. greater than 32 bits, in many current processors) the amount of storage allocated to track the PC of each instruction increases.
Some processor instruction set architectures (ISAs) define delayed control transfer instructions (DCTIs). A control transfer instruction may transfer program execution flow (either conditionally or unconditionally) to a target address. A DCTI transfers execution after the next instruction in the program flow (subsequent to the DCTI). The subsequent instruction is said to be in the delay slot of the DCTI. Typically, processors that implement an ISA that includes DCTIs track, for each instruction, both the PC of that instruction and the PC of the next instruction (the NPC) to facilitate delay slot handling. If a DCTI is taken (transferring program execution flow to the target address), the DCTI may update the NPC of the delay slot instruction. Thus, processors need only be able to locate the delay slot instruction of the DCTI to update the program counters when both the PC and the NPC are tracked. However, tracking both the PC and the NPC of each instruction increases the amount of storage allocated for PCs.
In fine grain multithreaded processors, each instruction in the pipeline may be from a different thread than adjacent instructions in the pipeline. That is, for a given instruction is a given pipeline stage, instructions in a pipeline stage immediately before and after the given pipeline stage may be from different threads. Accordingly, the PC and NPC of each instruction may typically be transported down the pipeline of the processor. Furthermore, any buffering that may be implemented within the pipeline requires storage for both the PC and the NPC of each instruction (or restrictions on the contents of the buffers in the presence of DCTIs in the buffers and logic to properly propagate PCs/NPCs through the buffers).